We take a look at how these amazing chips work.
In Digital Logic we have two broad classes of circuits. They are called Combinational and Sequential Logic Circuits.
In an earlier article, we considered combinational logic circuits. Their logic output levels depend only on the present state of the inputs at that time. Any prior conditions have no effect on the output. That is, they have no Memory. Most digital systems are made up of both combinational and memory elements.
Memory elements are called flip flops, latches, bistable multivibrators and binaries. The designations flip flop and latch are used interchangeably. We shall use the term latch for the moment, because it is the commonly used term in digital logic. In the true sense, a latch is a level triggered device while a FF is an edge triggered device. A good example of an edge triggered device is the edge triggered JK FF which we shall look at later in this article.
The latch has two outputs which are the inverse or complements of each other. They are called Q and Q.
The Set-Reset Latch
The most basic latch is the Set Reset and all others are based on it. Its block diagram is shown in Figure.1
It has two inputs labelled Set and Reset and are generally referred to as S and R. These are sometimes called Set and Clear. The outputs are Q and Q.
NAND Gate Set-Reset Latch
A latch made up of NAND gates and its Truth Table are shown in Figure.2. The circuit is also called a Figure 8 circuit due to its shape like the figure 8.
One input of Gate.1 is used as the Set Input and the other input is connected to the output of Gate.2
Similarly, one input of Gate.2 is used as the Reset Input and the other input is connected to the output of Gate.1 The output of Gate.1 is the output of the latch called Q. The output of Gate.2 is called Q. Note very carefully from the truth table, that the NAND latch operates on logic ‘0’ or is Active Low.
When S = 0 and R = 1 the FF enters the Set State as shown in the truth table. That is Q = 1 and Q =0. When S on gate 1 goes to 0 the output goes to 1. Now both inputs to gate.2 are logic 1 and gate 2 settles into Q = 0. This change in Q makes the second input on gate.1 equal to logic 0. If S is returned to logic 1 the logic 0 at Q holds Q at 1. At the same time Q =1 holds Q at 0. The device is now in the Set state.
When S = 1 and R = 0 the latch enters the Reset state that is, Q =0 and Q = 1. R = 0 makes the output of gate 2 equal to 1. Gate 1 now has both inputs equal to 1 and its output is held at 0. If R is now returned to 1 the 0 at Q holds Q at 1. At the same time Q = 1 hold Q = 0. The device is now in the Reset condition.
Set and Reset both low
The latch is not used in this state as both Q and Q both go High simultaneously, and the complementary state of the device is lost. If both inputs are raised High simultaneously, the gates race each other and the output cannot be predicted.
Set and Reset both High.
The latch does not change from whatever state it was in prior to S = R = 1. This is called the Memory State.
- S=R = 0 Not used as both outputs go high and the complementary feature of the device is lost.
- S=0 R =1 Causes Q =1 It remains here even after S returns to 1. Called the Set State.
- S=1 and R =0. Causes Q =0 It remains here even after R returns to 1. Called the Reset State.
- S=R=1 Remains in whatever state it was in prior to this input condition. Called the memory state.
A good understanding of the SR latch is useful in order to understand the operation of all other memory devices.
An alternative representation of the NAND latch is shown in Figure.3. The bubbles on the S and R inputs emphasise the fact that the inputs are active Low.
NOR Gate SR latch
A latch made up of NOR gates and its Truth Table are shown in Figure.4. It is similar to the NAND circuit except that the Q and Q have reversed positions. Unlike the NAND circuit the inputs are active High.
- S = 1 R = 0 Sets the latch to Q = 1 and Q = 0 Remains in this state even after S returns to 0. Called the Set State.
- S = 0 and R = 1 Sets the latch to Q = 0 and Q = 1. It remains in this state even after R returns to 0. Called the Reset State.
- S =1 and R =1 Not used as both outputs go low and the complementary feature of the device is lost. If both inputs are simultaneously made low, the gates race each other and the output cannot be predicted.
- S = 0 and R = 0 Remains in whatever state it was in, prior to the input condition. Memory state.
SR latch with Enable
The circuit and Truth Table are shown in Figure.5
The circuit is the same as the NAND latch with S and R and Q and Q. It is composed of Gates 1,2,3,4. Gates 1 and 2 control the data to gates 3 and 4 by the Enable (EN) input. Gates 3 and 4 are enabled by making EN High. The data at S and R are inverted and passed to S and R.
When EN is Low any inputs to S and R gives no change. When EN is High and S = R = 0 there is still no change. Note the truth table is the opposite of the normal NAND latch.
- When EN is low any input to S and R gives no change.
- When EN = 1 and S=R= 0 there is still no change.
- When EN = 1 and S = 1 and R = 0, S = 0 and R =1 giving
Q =1 and Q = 0
- When EN =1 and S = 0 and R =1, S = 1 and R = 0 giving
Q = 0 and Q = 1
- When EN =1 and S=R=1 both outputs go High and the complementary feature of the device is lost.
The data should not be changed when EN is High.
The D Latch
The D Latch is derived from the SR latch discussed above. The circuit and truth table are shown in Figure. 6. An inverter is connected between the set input and the reset input. The resulting single input is labelled the D or Data input.
This arrangement makes the set and reset inputs at opposite logic levels. When EN is 0 The output does not change for any value of D. When D =1 and EN goes High S =0 and R =1. This sets Q to 1 and Q goes to 0. The device is now in the Set state.
Alternatively, when D = 0, S=0 and R=1, and EN goes High
S =1 and R =0. This sets Q to 0 and Q goes to 1. The device is now in the Reset state.
Figure.7 is a D latch in an IC package. It works just like the above circuit and has the same truth table.
Edge Triggered D Flip Flop
Figure.8 shows an edge triggered D Flip Flop in an IC package. Note that this device is called a Flip Flop and not a latch due to the edge triggering.
Input data is transferred to the output when the proper edge is present on the clock input.
Master – Slave Flip Flop
The Master- Slave uses two clocked Flip Flops as shown in Figure.9. The one on the input side is the master and the one on the output side is the slave. The outputs of the master are used as the set and reset inputs to the slave.
When The CLK switches to 1 the output of inverter 1 switches to 0 and the output of inverter 2 goes to 1. The master is now enabled to read the data S1 and R1. Q1 and Q1 respond accordingly. The 0 at the output of gate 1 disables the slave.
When the CLK goes to 0 the output of inverter 1 goes to 1 and the output of inverter 2 goes to 0. The master is now disabled and the slave is turned ON. The data at Q1 and Q1 is then passed on to the output of the slave.
Master -Slave JK Flip Flop
The block diagram and truth table for a master-slave JK FF in IC form is shown in Figure.10. The circuit has two data inputs called J and K. These are just like S and R in the earlier circuits. It has a clock lead marked CLK, a pre-set lead marked PST and a clear lead marked CLR. The device has two parts. The FF on the input side is the Master and the one on the output side is the Slave.
- When J = 0 and K = 0 the device does not change state and is in the memory state.
- When J = 1 and K = 0 Q = 1 and Q = 0 and the device is in the Set State.
- When J = 0 and K = 1 Q =0 and Q = 1 and the device is in the Reset State.
- When J = K = 1 the device Toggles into the complement of the previous state.
In each case the J, K inputs are set appropriately and the clock moved Low, High, Low.
The device can in be used in the toggle mode by Connecting J and K to +Vcc and moving the clock from Low to High to Low.
NAND Gate latch
Set up the circuit shown in the schematic for the NAND gate latch. Note that the S and R inputs are active low. The 10K resistors ensure a steady voltage to S and R. When power is applied the device will wake up in a state corresponding to the positions of the switches A and B. Check out the truth table with the LEDs as shown. Use green for Q and red for Q.
NOR GATE latch
Set up the circuit shown in the schematic for the NOR gate latch and check out its truth table. Note the Q and Q have reversed positions from those of the NAND latch. Check out its operation with the truth table.
SR Latch with ENABLE
Set up the circuit shown in the schematic. Use two ICs to reduce the number of wires around a single IC. The inputs to gates 3 and 4 are controlled by the outputs of gates 1 and 2 and their inputs are the inverse of the inputs to gates 1 and 2. These can be easily checked by placing a logic probe on the outputs of gates 1 and 2. If this is not available, two LEDs can be used. Note when EN is low the circuit does not respond to any changes in S and R.
Check out the operation of the circuit with the truth table.
Set up the circuit shown in the schematic. Three ICs are used to reduce the wiring on a single device. Gates 1 and 2 are from one IC and Gates 3 and 4 are from a second IC. The inverter is from a third IC. When EN is 0 the circuit does not respond to D.
Check out the operation of the circuit with its truth table.
A D latch in a 7475 IC package is also shown. It operates just like the one described.
Edge triggered D Flip Flop
Set up the 7474 edge triggered D flip flop as shown in the schematic. The device is positive edge triggered. Note the data is transferred to the output, only on the positive transition of the clock. The PST and CLR should be disabled for normal operation by connecting them to +Vcc. Try out the PST and CLR by connecting each separately to 0V.
Master-Slave JK FF
Set up the circuit shown in the schematic. It uses a 7476 IC. A debounce circuit is used for the clock switch. It should be built on a small circuit board or on a piece of vero board. Check out its operation with the truth table.
When J=K=1 the device toggles, that is it goes into the complement of the previous state. If J=K=1 and CLK is connected to a very low frequency square wave, for example 1Hz and amplitude about 5 volts the toggle can be observed.
If this is not available set J=K=1 and operate the CLK from Low to High to Low.
The LED on the debounce circuit monitors the Low, High, Low transition of the clock.
The PST and CLR should be disabled for normal operation by connecting them to +Vcc. Check out the PST and CLR by connecting each to low (0V) on their own. Note that the debounce circuit is a good application of the SR latch.