Let's show you how these versatile counters and registers are used in everyday electronics from test equipment to timer circuits.
Counters
Now that we have covered Flip-Flops, and shown how they can be used as memory locations, perhaps it's time to talk about what we can use that memory for. One early application of digital logic, and indeed the first digital logic device I bought was a Digital Frequency Counter used for servicing CB radios.
Something amateur radio and electronic nerds tend to do is to always open the box for a peek inside at how the thing works. So, inside the box I found about thirty (yes ~30!) TTL ICs and six 7-segment displays, plus some analogue and power supply parts.
The basic operation was to amplify the RF signal to a sine wave large enough for the first TTL IC to convert into a logical square wave. The 'FAST' TTL could work up to 50MHz which was the stated limit of the primitive DFC, 'Digital Frequency Counter'.
The first task was to divide the frequency by 10 leaving us with a maximum of 5MHz which was within the range of most TTL ICs. The divider IC was a 4-bit BCD (Binary Coded Decimal) counter, probably 74LS92 or similar which divides the input by 10. (÷10)
Then there were six more BCD counters, connected in 'cascade' meaning that whereas each could count to 10, together the six could count to 100,000, well 999,999 before there was an overflow error. The outputs of the counters were fed to a set of six latches, i.e. memories, that held the value of the count at the end of one count period, which happened every 0.1 seconds or 100mS.
So if we were to look at 27,125,000Hz, a HF CB radio channel, divided by 10 results in 2,712,500Hz, then counting that frequency for 100mS would give us a number of 271250 in the latches.
The job of the latches is to hold that value while the counter begins counting for another 0.1 seconds. In fact the counter counts for 0.1 seconds and then does its homework during the next 0.1 second so the display only updates every 0.2 seconds.
The latches then fed six BCD decoders that in turn feed the 7-segment displays, resulting in a screen display of [271250]. The display also had two LED decimal points hard wired to add decimal points to the reading to result in [27.125.0] if everything was calibrated correctly and the weather wasn't too hot or cold which affected the accuracy. The counter was most accurate after reaching operating temperature.
More recently, but still quite a long time ago, the whole box of ICs was converted into a single chip, optionally feeding an LCD instead of the 7-segment displays. (Look up ICL7216 DFC IC).
Yet somewhere, an engineer needs to know what is going on inside the IC so instead of 27MHz, a better DFC can be designed to read up to maybe 27THz, that's 27,000,000,000,000Hz!
Asynchronous Counters
Therefore let us begin with some simple counters that are known as 'Asynchronous' or 'Ripple' Counters. The term ripple is not how it works, but the problem it has which we will soon get to.
When a 'D'-flip-flop has the !Q output fed back to the 'D' input, it becomes a toggle meaning that the output alternates with every clock pulse. By also feeding the !Q output to the clock input of another 'D'-flip-flop, the second will change as if the output from the first was a clock pulse.
However as it takes two clock pulses to cause the first flip-flop to generate one output pulse, the second flip-flop clocks at half the rate of the first. Therefore adding another flip-flop results in it counting at half the rate of the second, and so on for as many flip-flops as you like.
Adding flip-flops one after another is called cascading, especially when they come in an IC containing 2 x 4-bit counters, cascading the two results in an 8-bit counter in a single IC.
You may remember that a binary number can count to 2n, where 'n' is the number of bits. Therefore 28 becomes 256, meaning that an 8-bit counter can count from 0 to 255. What happened to 256? Remember that even in decimal, the number '10' requires another column and you can only count from 0 to 9 in one column, and that's a count with ten numbers!
Our next circuit [1] shows a 4-bit asynchronous counter using 'D' flip-flops. In this configuration it is an 'Up' counter, in that on reset it has a binary output of 'ØØØØ' which can be written as ØØØØb or in any of many other 'Binary' formats. The 'Timing Diagram' or 'Logic Analysis' shown below the circuit, shows what happens to each output when a clock pulse arrives at the first flip-flop.
The circuit [1] shows the Least Significant Bit (LSB) on the left, which is the correct way when the signal flows from left to right, as we read, but for numbers we are used to seeing the LSB on the right. The circuit shows the Most Significant Bit (MSB) on the right, so you need to remember that when interpreting a binary number in a circuit. (ØØØ1 => 1ØØØb)
Of course, we may need to build a counter that counts down, perhaps for an AFL game timer to blow the siren. The following diagram [2] shows a 4-bit asynchronous Down counter, built from the previous circuit simply by changing from the !Q to the Q outputs.
If you look at the timing diagram [2] however, you might realise that outputs of an Up counter simply need to be inverted to make a Down counter, and this method is also used at times, where the outputs are simply inverted by four 'INV'erters.
Ripple Problem
Asynchronous counters have a problem as the speed of counting is increased. Each flip-flop or stage can only change after the previous stage has changed. This means there is a short time delay called the Propagation Delay, that is the difference between receiving the conditions to change, and completing the change; [3] shows the problem by 'zooming in' on the 8th clock pulse and the changes in the 'Q' outputs, based on the Up Counter in diagrams [1].
The top Timing Diagram shows the full count in the top 5 timelines. With the area of interest highlighted at the point when the count changes from '7' to '8'.
Initially the code reading (right to left) from Q3 to Q0 gives us Ø111b or '7' decimal for one propagation delay after the clock pulse. This means that anything reading the value faster than one delay would read '7' when it should already be reading '8'.
Then when the second output Q1 changes, the code we would see would be Ø11Øb, decimal '6' and anything reading the value just short of two delays therefore would read '6' when it should expect '8'.
In short, anything reading the counter faster than the counter can change could get four different values depending on how fast it is. (7,6,4, or 0). An 8-bit counter could give 8 unexpected values over a period of 8 propagation delays. (It is a good exercise for students to work out what the incorrect values would be on an 8-bit Ripple Counter, in hexadecimal or decimal.)
Therefore Asynchronous counters are only used for slow systems or systems with bi-phased clocks. (Not going into them right now!)
Synchronous Counters
Synchronous Counters have the same clock pulse arrive at every flip-flop at the same time, hence the claim is that they are synchronised. Most of the circuits we prefer to use will be synchronised to allow them to work in a much larger and faster system.
Reviewing the same counters in a synchronised form, we should first look at [4] and [5]. The first feature you should note is that the clock goes to every flip-flop. The next feature of both circuits is that JK flip-flops have been used, wired as Toggle flip-flops with J and K wired together. The first input is wired to logic '1' so it must toggle when every clock pulse arrives.
Flip-flop 2 (for Q1 output) will only toggle when J & K are high, which is when the first Q is high [4] counting up, or when the first !Q is high [5] counting down.
Flip-flop 3 (for Q2 output) uses an AND gate to raise its own J & K when the Q outputs of FF1 and FF2 are high in the up counter, or the two !Qs are high in the down counter.
The second AND gate ANDs the output of the first AND gate to the output of Q2 in the up counter or !Q2 in the down counter. i.e. the final bit only changes when all three previous bits are set, in the up counter, or reset in the down counter.
The Up counter and the Down counter therefore operate on the same basic circuit by swapping connections from Q to !Q. This allows us to consider another circuit that can count either up or down by swapping all of the Qs with !Qs using a combination logic control. Such a circuit could count people entering a club and count down when they leave. Other applications would include CNC Machining stepper motor control and positioning.
Synchronous Up/Dn Counter
This circuit [6] is the same as the previous two circuits except the options of Up or Down counting can be selected via an added pin and some simple combinational logic.
By now we might expect that this logic would be easily read by our readers who have followed along with us. If it is still not making sense for you, maybe read the previous columns again with these new applications in mind. It is always difficult to learn material if you cannot see a future use for it.
The logic uses each OR gate to apply a toggle input to the respective flip-flop when the 'Up' pin is logic '1' and also the respective 'Q' is high, OR when the 'Up' pin is logic 'Ø' and the respective '!Q' is high.
Each set of the two AND gates and single OR gate passes it's logic on to the next set so each flip-flop operates when all previous flip-flops are Set for counting Up or Reset for counting Down.
Preset and Clear
The terms Set and Reset are often used but as they are inherent in the SR flip-flop, you will often see other terms used to avoid confusion, (Not always achieved!) or to better define a pin function.
Preset (PRE) and Clear (CLR) are often used on JK types although we have left them off our circuits thus far. In 4-bit and 'more-bit' counters there are times when the counter should start on a certain number, and count up or down from that number. That function may work in several ways either setting that one flip flop to a high using the 'PRE' pin or a low by using the 'CLR' pin, or on appropriate ICs, in Data Set mode by presetting the flip-flops to whatever was on JK Inputs at that time.
The 'CLR' may also be used to reset the clock or counter back to Zero, ØØØØb.
The circuit [7] uses a simple AND gate (the one below the main circuit) to place a logic 'Ø' on each of the reset (clear) pins, (RST) when the AND gate is gated. The flip-flops shown require a logic 'Ø' to operate which is defined on the symbol both by the 'Overline' above the letters 'RST' and by the circle shown below 'RST' outside of the symbol box. (An 'overline' is an 'underline' above the text!)
You should be able to determine what value would cause the reset/clear to occur by recognising what number was counted to cause the reset. For example a BCD, or Binary Coded Decimal number only counts from 0 to 9, before resetting, and a digital clock would be required to reset the seconds when it reaches 60, or 6 in the tens column and 10 in the units column, or even 12 or 24 hours. Counters don't only count binary numbers!
Ring Counters
A Ring Counter is a very simple device [8]. The series of D flip-flops are connected in a completed circle by connecting the last 'Q' output to the first 'D' input. Outputs can be taken from one or more 'Q' outputs. An input can be injected for example in the 'D' input shown in the circuit, or the circuit can be initiated by the Reset/Set pins as shown at the 'RST' pin. In this case the first flip-flop would be Set and the remaining three Reset. Clock pulses would then cause all of the flip-flops to turn on in sequence.
Twisted Ring Counter
A variation of the 'Ring Counter' known as the 'Twisted Ring Counter' or Johnson Ring Counter' [9] doubles the count by connecting the last '!Q' to the first 'D' input. This requires the number of flip-flops to change twice in the sequence resulting in a count of twice the number of FFs. You may have seen science fiction movie Robots with LED eyes that scan side to side or wide then narrow. These were almost certainly done using ring counters.
Quadrature Counter
A Quadrature signal is a pair of square wave pulses offset by half the period of one pulse, being a quarter of one complete square wave. One application is to use a rotary encoder switch that counts pulses but causes the counter to count up or down according to the direction of rotation of the switch.
Stepper Motor Driver
Another application of the Quadrature logic circuit, is used today in Stepper Motor Drivers. The circuit [10] shows two flip-flops connected in a twisted ring arrangement but with the outputs taken by a set of four AND or NAND gates.
Ignoring the Driver Outputs which are designed depending on what type of Stepper Motor to drive, you might recognise the clock input as the 'STP' (Step) input. The Stepper Motor controller also has a 'DIR' (Direction) control which uses a combination logic circuit invert one of the timing waveforms, which causes the motor to step backwards or opposite to whatever direction the other option caused.
Registers Parallel and Serial I/O
Computers first stored their data in 4-bits, then 8-bits which was very popular for many early years of computing. Then designers went to 16-bits, 32-bits and now 64-bits has been the standard for some time.
The number of bits determines the size of data that can be acted upon with a single clock cycle, but the bit-wise size of the data doesn't always help greater speed.
Sometimes data must be sent, and of course received, in serial form, 1-bit at a time.
Both Serial and Parallel methods have their purpose, strengths and limitations, but as Computers use parallel data internally, we often need to convert between Serial and Parallel data. We can do that, and many other tasks with Registers and Latches.
Shift Registers
A computer register is a place to store data, usually intended as a single character, code, or number, but sometimes as a part of a larger piece of data and other times as a number of individual bits of data, such as in flag registers. In fact, it is always a binary sequence open to interpretation.
The first thing we need to understand, is how data gets into and out of registers. If we imagine our data storage as a set of boxes [11], each capable of holding one bit of information. The four boxes in this demonstration can only hold 4-bits, one bit in each box. The data can be all placed in the boxes at the same time, 4-bits dropped into the boxes in parallel which can be called Parallel Input (PI).
If the boxes are emptied together then that implies data output in parallel, called Parallel Output (PO).
Now although our analogy doesn't show this option, assume that the data bits are all lined up on a shelf, so they can be pushed along and into the boxes one step (or clock cycle) at a time. This is an example of Serial Input (SI), and another set of 4 steps for the 4-bit register will remove the data from the boxes, giving Serial Output (SO).
Combinations of these actions create the four basic types of Registers, SISO meaning Serial Input Serial Output, PIPO meaning Parallel Input Parallel Output, SIPO meaning Serial Input Parallel Output, and what you would think is the final option, PISO meaning Parallel Input Serial Output.
Some registers are able to perform multiple actions with suitable commands via command pins, and one type, called the Universal Shift Register, can take its input as serial or parallel, and give a serial or parallel output.
Before we show how these registers can be created, most computer registers would also allow the serial data to be Shifted Left meaning through the Most Significant Bit (MSB), or Shifted Right meaning through the Least Significant Bit (LSB). These processes are for Mathematical purposes, such as multiplication. Therefore the process may cause a 'Carry' or require a 'Borrow' which requires the Register to have two more bits than the number of data bits.
One last function that a shift register can perform is to 'Rotate' or 'Roll' left or right in which case the data exiting the register at one end is placed back into the register at the other end. Roll left takes the MSB from the left side and pushes it into the LSB with every bit shifting left in the process.
Serial In Serial Out Register
The Serial In Serial Out Shift Register (SISO) is used where the data is required along a wire pair, or single wire with ground, or in a Radio Data Link, where the speed it is received may be incompatible with the speed it must be sent at. For example a slow baud rate perhaps even 300 baud has to hitch a lift on a fast carrier, so apart from packeting the data, it must be sent at a Baud rate to suit the fast carrier, in bursts due to the data arriving much slower than it will be sent.
Note: For any real Baud Rate changing system, the data would be converted into parallel and placed on a stack to await transmission at which time it would be converted back to serial data.
Diagram [12] shows how serial data can be fed into a register where it is held in flip-flop memory until it is resent. The circuit shown also shows individual Q outputs to allow us to 'see' how the timing diagram shows a logic '1' being passed through the register. Instead you can change the data input before each clock pulse and draw your own timing diagram to follow how it works.
First In First Out
The circuit [12] has only one direction making it a FIFO arrangement that means that the First data In becomes the First data Out, (FIFO). It is possible to create a Register that works on Last In First Out, LIFO, also known as a Stack, which is more common in parallel data storage.
Serial In Parallel Out Register
The circuit we have just described shows the Serial In Parallel Out Shift Register (SIPO) as well as the SISO, as we have used the 'Q' outputs for other purposes but they are also the Parallel Outputs. In a Parallel Output Register the last data usually remains in the register after the last data has been sent, unless it is 'Cleared' by the register.
Parallel In Parallel Out Register
The circuit [13] is really a set of individual 'D' type flip-flops that share nothing except for a common clock signal. Data on the four 'Data' pins is passed to the four 'Q' Output pins D0->Q0, D1->Q1, etc. whenever the clock pulse triggers the exchange of data from the 'D' side to the 'Q' side.
Parallel In Serial Out Register
Our circuit [14] shows the almost complete set of functions in a single Shift Register. While it would normally be called the Parallel In Serial Out Shift Register it has a separate 'LOAD' pin which is active low meaning that it operates when the pin is pulled low. The 'LOAD' pin uses the Preset 'PRE', and Clear 'CLR' pins of the JK flip-flops.
When NANDed with the LOAD signal, a logic '1' on D0 for example will cause the 'PR' pin on FF1 to preset Q0 to logic '1'. A logic 'Ø' on D0 would result in the 'CLR' pin to clear Q0 to be a logic 'Ø'.
This does not always require the clock to pulse unless the datasheet specifies a clocked Set/Reset. (i.e. clocked PRE/CLR)
Once the data is set for the 4-bits, clock pulses can be used to shift the data out through the 'Serial Out' pin.
Note: In this circuit there is no 'CE', (Chip Enable) being used but as the clock should be running continuously, it would be expected that some other form of control would be used to decide exactly when data is shifted in or out of the register allowing the system to make sure it is there when needed, and the following circuit is ready to receive the data so it is not lost.
Universal Shift Registers
We are spoiled in that the Register ICs we have available to us tend to have more options than we typically need in a single design. Here we have one type of Universal Shift Register [15] which can do just about all we would ever need from it.
The bottom half of the circuit is the same as the circuit we have just described taking a parallel input directly into the IC, possibly without any clock necessary depending on the flip-flop design.
The combination of two NANDs, an AND and an Inverter feeding each set of 'JK' pins allows all four types of Shift Register in the one device, while allowing a choice between Shift Left and Shift Right.
Using external logic, the shift outputs can be stored into a 'Carry' to be shifted into the shift inputs as a 'Borrow', and similarly Rotate Left and Rotate Right can be implemented.
These functions come close to what is required in a Computer ALU; Arithmetic Logic Unit.
74595 SERIES
I have chosen this device to discuss as it has been used in several past Diyode projects, and has become a popular device for Arduino (etc.) expansions. The 74595, and similar numbered TTL and CMOS devices use a minimum of three pins up to a maximum of five pins in allowing 8-pins of output, and with a little bit of daisy-chaining, the outputs can be expanded to as many bits as you care to send, subject to some eventual limits in driving the serial data bus and control pins.
First, we must explain that the 74595 series of devices all have the same pinouts for the same package [16]. Various families of logic may be used to suit your own use with any having the 'C' between the '74' and the '595' being CMOS types, 'H' meaning 'High speed' and 'V' meaning advanced, so a SN74VHC595 is an advanced high speed CMOS type.
CMOS types have the advantage or working on 3.3V inputs and up to 7V outputs, more on some types.
For more information, I recommend downloading one or more of the many data sheets for various 74595 types and reading through them.
SHIFT-REGISTER
One half of the 74595 is a serial in, serial and parallel out, shift register, like those we have just covered, requiring three input pins, pin-14 'SER' is the 'Serial in', pin-11 'SCK' is the 'Serial Clock' which is active on the rising edge of the clock pulse, and pin-10 '!SCLR' is the 'Serial Clear'; an inverted signal to reset the serial input when pin-10 is low.
These three pins can be driven by an Arduino, (or other microcontroller) connecting pin '!SCLR' to Vcc if it is not to be used. The function of the '!SCLR' is to clear all of the flip-flops plus the Q'H Serial Out, which is handy to clear a whole string of 74595's serial inputs with just one clock pulse.
TRI-STATE LATCH
The outputs are latched 'D' type flip-flops followed by Tri-state buffers, requiring two input pins. Pin-12, 'RCK' is the 'Clock' to the Output Latch, sometimes called the 'Storage Register' which is a positive edge triggered clock. Both clocks can share the same Arduino pin to be driven as a single clock, but the latch outputs will update one clock pulse after the serial Shift-Register.
Many applications may accept this but typically the programmer would prefer to load the serial register, and then update/enable the latches (storage register).
Pin-13, '!G' (the Gate) enables the outputs when '!G' is logic low. Then whatever logic is applied to the latches from the Shift-Register will be transferred to the buffer outputs, at the supply voltage of up to 7volts DC on this CMOS device. TTL devices such as the 74LS595 will expect a +5V supply.
If '!G' is logic high, then the outputs will be a high impedance so no logic levels will be seen at the outputs. '!G' can be held low, and whatever changes occur at the inputs of the latches, will be latched on the 'RCK' clock pulse, and thus be applied to the outputs 'QA' to 'QH', or 'Q0' to 'Q7' meaning the same pin numbers but named depending on the data sheet nomenclature.
CASCADING 74595's
If more than eight outputs are required, one 74595 can be connected to another by connecting the Serial Output Q'H pin-9 of the first 74595 to pin-14, 'SER', the Serial Input of the next 74595.
The three to five control pins from the microcontroller can be connected to each of the 74595's up to the maximum fan-out for the microcontroller output and 74595 input load. In this way, almost any number of 74595s can be connected in 'series cascade', as long as they can be driven by the micro!
WHERE TO FROM HERE?
If you have not read parts 1, 2 or 3 of our Logic Gates series, then we encourage you to go back and read those. You can learn more about the 74HC595 Shift Register IC by reading our What The Tech article in Issue 005.
To see the 74HC595 in a practical application, check out our Mega Digits Display System project in Issue 005. Our ATDEV For ATtiny programmer project from Issue 014 is another good example.
Part 1: Digital Logic Gates Explained