An in-depth look at some basic devices that are often bewildering for the beginner to digital electronics.
While most of us go straight to microcontrollers when we think of digital electronics, the truth is that this trend is relatively recent. While out of fashion, discrete circuit construction still has a valid and useful place. Microcontrollers are getting cheaper, and an ATtiny85 can do a lot of the jobs that someone could spend hours building a circuit for. However, sometimes the simplicity of a dedicated circuit is desirable. They can be more rugged, never have hidden code bugs, and do not hang or freeze. Not that most modern microcontrollers do that anyway. Some people also struggle with coding languages, despite their other abilities. On top of all that, there is quite a lot of value in knowing how things work, even if the direct need to implement such a circuit never presents itself.
One such fundamental building block is the latch or flip flop. We discuss the flip flop on a somewhat regular basis, as it underpins the operation of the NE555, an integrated circuit (IC) we use often. One of the most versatile and widespread ICs in our inventory, it was released to market by Signetics fifty years ago this year (although designed the year before). However, flip flops and latches are available as ICs, to be used on their own. There is quite an array of them, too. D, JK, SR, tri-state, and some are called latches while others are called flip flops.
What does it all mean? We will discuss the main terminology, and cover what makes each device type unique. We will also highlight several specific ICs that are readily available on the domestic market. This point is important, because there are a great many devices around that fall into these categories. However, only some are available from suppliers that most makers can access.
Anyone can order from Element14, for example, or RS Components if you are willing to buy a minimum quantity. These companies are trade, engineering, and commercial suppliers. They have inventories hundreds of times the size even of the biggest domestic retailers. Almost anything made anywhere in the electronics and related industries can be bought from them. However, they are aimed at trade customers. If you don’t already know what you want, what it is called, and how to use it, these suppliers are not the best idea.
A Flip Flop or Latch is the name of a circuit arrangement, not necessarily a device. They can be made from discrete components, however are normally obtained as dedicated ICs. It is possible to make one from transistors, but this is uncommon. If they are going to be made rather than bought as a dedicated device, it is usually with gated ICs such as OR and NOR gates. A practical reason for doing so may be to make use of otherwise unused gates within, say, an quad OR gate, rather than introducing a new IC to take up space on a PCB. The main reason for showing them in the following pages as individual gates is for the sake of understanding.
A flip flip or latch usually has two inputs and two outputs. Two two outputs are the opposite of each other: When one is high, the other is low. One is labelled as ‘Q’, while the other is labelled as ‘Q’. In maths, BAR denotes the inverse, or opposite. So, if Q is high, Q is low. If Q is low, Q is high. Flip flops and latches are bistable, meaning they have two stable states. This is reflected in the outputs being either high or low. They can be used to store information that was present at a given time. 'Storing information' includes situations such as turning momentary signals from a sensor into an on or off constant signal.
LATCH VERSUS FLIP FLOP, AND OTHER TERMINOLOGY
The two terms are often used interchangeably in forums, videos, and even some textbooks. However, there is a defined difference. A latch is active all the time: That is, any change in the inputs produces a change at the outputs immediately. A flip flop, on the other hand, is a clocked device. It changes only when a certain signal is given to a dedicated pin. So, in the case of the SR latch shown ahead, as soon as the input states change on the S and R inputs, the outputs change state.
In an SR Flip flop, the output states change according to what the input state is only at the moment the clock signal is received. Input changes at any other moment do not count. This terminology is becoming more common, but is not universal. The terms have been used interchangeably for a long time. If you conduct your own further reading, you will likely encounter this problem.
A device may be described as 'Active High' or 'Active Low'. This is not limited to flip-flops and latches; it applies to other digital logic and even some analog devices. 'Active high' means that under normal circumstances, the inputs are held low, and a change to high controls the input. 'Active low' means that the inputs are normally high, and a change to low controls the input.
The term can apply to outputs as well, where active high would describe an output that is low until activated, at which point it changes to high. Active low means an output that is normally high until activated, at which point it will go low. We do not describe the outputs of flip flops and latches this way because there are two outputs. One is always the opposite of the other, high when the other is low.
There is also the naming of tables. You may have encountered 'Truth Tables' when reading about logic gates. These are a table which shows 1 for high and 0 for low, for a given set of circumstances. At the left of the table are the inputs, usually labelled 'A' and 'B', then with other letters of the alphabet as needed.
The next column is often labelled 'Y', and represents the output, with 'X' and so on if there is more than one output. The result is a visual indication of what the output does for a given set of inputs.
When discussing latches and flip flops, these tables are called 'Transition Tables'. Other names are 'Characteristic Tables' and 'Excitation Tables'. They will look a lot like truth tables, but outputs are shown as Q and Q, and there may be a column for 'enable', or 'clock', as relevant. The principle is the same, however.
One side shows the inputs, and the other the outputs. However, they can be confusing for people unfamiliar with them. The outputs are shown as 'Q' and 'QNEXT' or 'Q+'. Q is the current state of the Q output before the listed input combination, while QNEXT or Q+ is what the Q output will be after that input combination. Q is always the opposite of Q, so it is not shown.
The circuit symbols and transition tables for each device are presented together as appendices at the end of the article, so they can easily be compared and viewed side by side.
VERY BASIC LATCH
One of the most basic latches that can be made is so basic that it is almost useless. However, it does help in understanding as things get more complex. It starts with a regular OR gate. If we cast back to either Elmo V. Jansz' Fundamentals in Issue 55 or Kids' Basics in Issue 56, the OR gate has two inputs and one output. The output will be high if either input one OR input two is high, OR both. The simplest latch is made by connecting the output to one of the inputs.
As soon as a logic high is received on input A, the output goes high. The output is connected back to the input, which now generates a high on input B. This means that the output stays on, because it feeds back instantly to be an input. Because the OR gate works when either input is high, the output feeds back to the B input even after the signal on the A input is removed. It is latched, and will stay so until power is removed. That last point is why the circuit is almost useless. It could have a circuit built in to interrupt power on command, or a pushbutton switch to manually do the same job. However, an arrangement of gates which already does this would be better.
While we said that this circuit is almost useless, because of the need to manually reset it, there are some practical applications. It would apply in any situation where a momentary event such as a door opening (with a sensor) needs to be recorded, and acknowledged by a person. Having a manual reset button in this case is not a bad thing - it serves as the manual acknowledgement, where the circuit can only be reset deliberately.
THE SR ARRANGEMENT
The most basic usable flip flop and latch arrangement is the Set-Reset, or SR. The SR latch is the easiest to describe. A basic one is made with two NOR gates. The NOR gate is a logic gate where, for the output to be high, neither input one NOR input two can be high. They must both be low. The truth table for the NOR gate next to the latch diagram should help you follow along, but note that it is for a single gate alone, not the latch as a whole.
To explain its operation, we have to assume that the Q output is high at first. In reality, with no active inputs, the NOR gate outputs will both go high, although component tolerances and internal factors means one gate will do so before the other, on a fractions-of-a-second time scale.
Which one is not predictable, so devices have a bias built in. Others, as can be seen from product listings, have a preset input for user-selected control over which state the device powers up in.
With that in mind, consider the situation in the diagram as though nothing has happened yet. Also assume that these are active-high devices, as most we will deal with will be. At the start, output Q is high, and output Q is low. None of the inputs have been sent high yet.
The Q output is only high because it turned on slightly faster than the Q output. It won the race, and racing is a term you might even trip across when discussing logic that can have unstable states.
In the diagram section headed 'Initial State', you can see the high output of Q is fed to one of the inputs of the lower NOR gate. According to the truth table, this now has an output of 0 or low. It stays that way, too. The upper NOR gate has both of its inputs low. Until, in 'A', a high pulse arrives at one of its inputs.
Again according to the truth table for NOR gates, the output of this upper gate now goes low. As can be see in 'B', as soon as this output Q is low, the lower NOR gate now has both inputs low, and so its output, Q, goes high.
This happens very quickly, so in the diagram, the incoming high on the 'set' input is still there. This will be the case even for a very short input pulse. When the input pulse ends, in 'C', the lower NOR gate still has both inputs low, and so its output Q is still high, but it is cross-connected to the upper NOR gate, which consequently has one input high. According to the rules of a NOR gate, this upper gate has a low output, Q, because one input is high. This state is stable for now.
To make this state change, we start with an initial state again. This is the opposite of the first one, because the set operation has already been performed and the circuit is in the state it finished in before. That is also why we have changed colour for the high sections.
In 'A', a high pulse arrives in the Reset input. The NOR gate now has one input high and so the output, Q, must go low. In 'B', you can see that this removes the high that was being fed to the upper NOR gate and keeping its output Q low. The Reset pulse is still present, so the upper NOR gate now has two low inputs, and its output Q goes high in response. In 'C', you can see this is cross-connected to the lower NOR gate's input, keeping output Q low. This is the other stable state.
Whenever the Set and Reset inputs are both low, the Q and Q outputs cross-connected to the inputs keeps the state stable. Thus, even though the input pulses to set and reset are momentary, the other inputs to the NOR gates are constant. This is why the circuit latches on and stays stable.
There is one big problem with this circuit: A high on both Set and Reset at the same time causes unstable behaviour. This is called an 'invalid' operation, a 'restricted combination', or 'forbidden state', and needs to be avoided. However, it cannot be avoided with the SR arrangement. The D and JK arrangements do have protection against this. It is just helpful to understand the SR arrangement before progressing to the others.
The situation so far has been describing a latch. Latches are 'level triggered', which means that the outputs change state as soon as the level on the input changes correctly. The other term for this is 'Transparent', and that is the term you will see in any academic or engineering discussion. However, there is such a thing as an SR flip flop as well, where the outputs only change when an 'enable' or 'clock' signal is given. To do this, we need to add more gates.
Thankfully, this is quite easy to achieve. All that is required is a pair of AND gates. Looking at the truth table for an AND gate, both input one AND input two need to be high in order for the output to be high. The output of each AND gate is used as the input to the relevant NOR gate. One input on each AND gate becomes the Set or Reset input as relevant, and the other input on each AND gate is tied to the other. A single 'enable' input is now created. Only when the 'enable' input is high will the outputs of the NOR gate arrangement change. This is a flip flop, and is the basis of many data processing and storage systems. Note that the output still latches on and off: They are not only active with the 'enable' input, they behave exactly as before. The AND gates only change how the inputs behave, making them controllable.
This type of circuit is often called 'edge-triggered' because it is the rising or falling edge of the data going from logic low to logic high, or high to low, that causes the change.
So far, all of these circuits have been active high. However, the SR latch can be made with NAND gates, such that the inputs are normally high and are taken low to activate. This makes a logic 0 or low the input signal. The inputs are now shown as R and S, because they are inverted. The functionality is the same: Set changes the latch, and Reset changes it back. They are inverted because activating them demands sending them low, rather than high.
It is still possible to turn the arrangement into a flip flop. However, this time, the roles are reversed. The NAND gates form the latch as above, but this time it is OR gates forming the input gating. Because OR gates have a high output if input A OR input B OR both are high, an input is only given to the NAND gates if the EN-BAR input is low, and either the S or R inputs. In other words, the inputs, including the enable input, are all active low.
THE JK ARRANGEMENT
If you look through IC listings in, say, the Jaycar or Altronics catalogues, you may notice a distinct lack of SR flip flops or latches available. This is mainly because the invalid state issue of two high inputs, S and R together, makes the device less useful. Instead, some arrangement is required that means that either this cannot happen, or cannot cause a problem if it does. In literature around logic, you might see things like R = 1. This means that R is at logic 1, or high. The invalid condition for an SR flip flop involves S = 1 and R = 1 at the same time. Written properly, this is: S = R = 1. By putting them in one number sentence, the fact they are simultaneous states is made very clear.
The JK arrangement builds on the SR but interprets S = R = 1 as a command to switch the outputs, rather than as an invalid state. This is achieved with a NOR gate SR latch, and AND gates on the inputs.
The JK latch is often said to be a theoretical device. It is almost never built, and we were unable to find a commercially made IC that was a JK latch as opposed to a JK flip flop. There are few uses because most applications of the JK arrangement (and latches and flip flops in general) are centred on data processing. Lacking the ability to be commanded, the JK latch doesn't have a home in this application. We can think of one, however.
In household electrical circuits, many people will have experienced a two-way switch. This is where you can enter a room though one door, and turn the light on with a switch. Then, leaving through another door, turn off the light with a different switch. The order does not matter.
In electrical systems, this is achieved with a single-pole, double-throw switch, wired as in the diagram. Some systems have multiple switches which can turn on and off the light, but they require a specialised switch called an intermediate switch. The mechanism in these rocker switches rotates around the x in the diagram.
The JK latch provides one of several ways to implement this electronically. If you had, for example, LED lighting in a room or hallway, and wanted to control it with touch switches or IR sensors which give just a single pulse when activated, then any of the two-input latches are no good to you. Nor is the JK flip flop, unless you have a clock pulse constantly running. All of the inputs from the sensors can be connected, and both of the JK inputs connected together, and you have a two-way or multi-way electronic toggle switch. However, there are other (and probably better) ways of doing that. There may even be one in this article, if you look out for it.
The far more common use of the JK arrangement is with the addition of a clock ability, as a JK flip flop. This involves the use of triple-input AND gates, but we're no longer making these with individual gates anyway. You could make a JK flip flop from gates just for the sake of it, but it is impractical. A high on J and a low on K (J = 1, K = 0) sets the flip flop on the next clock pulse. A low on J and a high on K (J = 0, K = 1) resets the flip flop on the next clock pulse. Note that the J or K input has to be high at the moment the clock pulse takes place: there is no memory built in to capture a pulse that arrived between clocks. Like the JK latch, the JK flip Flop interprets J = K = 1 as a toggle command, regardless of whether it was in the set or reset condition. Again, the clock pulse must be present when the inputs are high for toggle to occur.
THE D ARRANGEMENT
The D arrangement is realistically simpler than the JK arrangement. It is an SR arrangement with the addition of an inverter, and only one external input besides the clock or enable, in the case of the flip flop. In the latch circuit, the SR flip flop can be seen clearly, with the addition of an inverter. Whenever there is a high on D, it is passed straight through to S, and inverted to be a low on R. This provides the S and R inputs, but only as long as there is a high on D. As soon as there is a low on D, the outputs toggle back. That doesn't sound very useful, and it isn't.
Most D arrangements are flip flops. They are often found in literature as 'Gated D latches' but we're sticking with the terminology we established earlier for the sake of consistency. Bear this in mind if you do your own reading. The presence of an enable input means that the output will now stay latched in whatever state it was in when the enable signal was removed: If the S input was high and the R input low as fed by the inverter, the enable input stops the signals charging.
Both the SR NOR and SR NAND flip flops work as D flip flops. The presence of the enable pin means that data storage is now possible. If a string of D flip flops is connected together, a serial-in, parallel-out register is created. At every clock pulse, the output of one flip flop is read as the input to the next. Whatever bit is present on that output, 1 or 0, moves to the right The incoming serial data is fed to the first input, with a high corresponding to a 1 and a low corresponding to a 0. Every four clock pulses, the parallel data can be read from the top of each output. The Q output is not directly used here, but it is functioning internally to operate the flip flops.
This is one of the problems with the terminology around latches and flip flops. The flip flop described above is often called a latch in the literature. This is because what we call a latch, with no enable or clock input, is not very useful and is rarely used. The word latch is applied to what we have so far called a flip flop, because there are more complex forms of D flip flop that have traditionally been denoted by that name. Many types of D flip flop also have the S and R inputs accessible, as well as them being fed by the D input. This gives extra control over the behaviour of the device.
To see this, it is best to view the NAND gate version. The difference between the two diagrams is the use of double- or triple-input NAND gates. In the version with two-input NAND gates, a classic D flip flop, enabled on the rising edge of the clock signal, is created. By using three-input NAND gates in place of some of the two-input ones, and adding some extra cross-connecting, the S and R inputs are now available.
ENABLE/ CLOCK PIN SYMBOLS AND
The symbol on any flip flop denoting the enable or clock pin is generally a < or >. This represents whether the action happens on a rising edge >, or falling edge <. The circuit symbol itself will tell you whether a device is active high or active low, by the use of the BAR symbol above the inputs, no matter what they are.
There are a variety of other latches and flip flops. They are either uncommon or specialised, or only slight variations of those discussed. If you go on reading about flip flops and latches, or start experimenting with them, you will probably find these terms.
One that deserves mention is the T flip flop. This is a JK flip flop with both inputs tied high. Note, that is a JK flip flop, not a JK latch. With the inputs held high, the enable or clock input becomes the active input. If used with a regular clock signal, it becomes a divide-by-two frequency counter. Strung together, a bunch of them would make a binary counter. Used with an irregular clock signal (perhaps a sensor input or touch switch), a T flip flop forms a single-input toggle, hence 'T' in the name.
MASTER SLAVE FLIP FLOPS
Because the JK flip flop has the outputs tied to the inputs, it can oscillate under some circumstances. The clock pulse on a JK flip flop must be kept as short as possible in order that a situation known as 'racing' does not occur. This is when the output goes high while the clock signal is still high, and because of the outputs being fed back to the inputs, the system goes haywire.
A solution is the master-slave JK flip flop. This is two JK flip flops connected in series, and fed from one common clock pulse, However, the second flip flop has an inverter between its clock input and the clock signal. The result is that the slave half, the second half, responds to the falling edge of the clock pulse. The outputs of the master, or first half, are fed to the inputs of the slave. This means that the final output on the slave side cannot change state until a clock cycle has finished.
Master-slave flip flops can also be constructed from D type flip flops. As noted earlier, what we have called a flip flop here for consistency is often called a gated D latch in other documents. This one responds on the falling edge of the clock pulse, but by adding an inverter to the clock input of the master as well, a positive-edge triggered device can be created.
OTHER FLIP FLOPS
The phrase 'flip flop' is sometimes applied in other situations. It is often used to describe any circuit whose output switches from high to low based on some input condition. However, many of these situations are not logic circuits, and whether or not the phrase 'flip flop' applies is up for debate.
Something as simple as a comparator could be considered a flip flop, if the inputs were spread far enough apart. However, there is no latching ability.
As soon as the high signal at the input is gone, so is the high at the output. A comparator circuit with feedback, and a way to interrupt that feedback, would get close to the operation of a basic SR latch. The circuit presented here is such a building block: It is the standard arrangement for a comparator with feedback, creating hysteresis. The hysteresis can be adjusted so that the behaviour at the output is nearly digital.
THE NE555 AS A LATCH
If all this talk of flip flops has made you think of the NE555, you are not alone. Discussion of the operation of that IC always involves the internal flip flop. While we usually think of this IC as one controlled by the charging and discharging of a capacitor, the venerable NE555 can be made to function as an SR latch. In its basic form, it needs a negative pulse to the trigger to set it, and a positive pulse to the threshold to reset it. However, with some external components, we can create a situation where both inputs are positive.
You might ask why this would be a desirable thing, when so many low-part count ICs are available to do the job? The answer comes in the ruggedness of the NE555. The common logic ICs are in the 74LS and 74HC series, which are 5V logic. The 4000 series are more forgiving, but still sensitive devices.
The NE555 on the other hand, is about as close to indestructible as an electronic component can get. It is highly tolerant of voltage fluctuations and most importantly, has a 200mA sink or source current capability on its output. Most logic devices, even ones capable of higher voltages up to 15V like some 4000-series devices, are limited to 10mA source, and some cannot sink at all.
The uses for flip flops and latches are too myriad to list without getting into an explanation of basic computing first. However, many simpler circuits use them too, and many makers have come across them at some point.
While this explanation has been quite compressed in the grand scheme of things, we hope you have a better understanding now of what flip flops and latches are and how they work, to help make sense of the information you find. Now the different types like JK and D are no longer a mystery to you, and knowing how each works should help recognise what is going on in situations where you see them.